(1) Field of the Invention
The invention relates to clock frequencies in peripheral devices and more particularly to running a peripheral device (slave) at a clock frequency different than that of a microprocessor (master), without using clock resynchronization.
(2) Prior Art
A microcontroller generally includes a microprocessor, memory, a peripheral module that provides communication, for example Universal Asynchronous Receiver/Transmitter (UART), SPI, and USB, and an interrupt controller. Peripherals are generally configured to exchange data with microprocessors through internal buses. A bus typically conveys data, address and control signals. One method of handling data buses for multiple peripherals is by multiplexing the signal.
FIG. 1 is schematic illustrating a prior art simplified microcontroller with system bus. Microcontroller 100 includes microprocessor 102 coupled to peripherals 104 and 106. The address bus, write data bus and read/write signal are combined for simplicity in system bus 108. System bus 108 includes multiplexer 110 that selects between data from peripherals 104 and 106.
FIG. 2 is a schematic illustrating a prior art simplified microcontroller with individual bus lines. Microcontroller 200 includes microprocessor 202 connected to memory 204. Address decoder 206 receives and decodes addresses from microprocessor 202 for memory 204 and peripherals 208-1 and 208-2. External bus interface 209 connects to microprocessor 202 through system address bus 210, system read/write 212 and system data bus 214. External bus interface 209 enables microcontroller 200 to interface to external components (not shown).
Address decoder 206 receives and decodes an address from system address bus 210, and issues a select signal on bridge select line 215 to bridge circuit 216, which then selects between peripheral 208-1 and 208-2. Bridge select logic 216 coordinates bus signals from system address bus 210, system read/write bus 212, and system data bus 214 with peripherals 208. Bridge circuit 216 also translates the protocol of the system bus into protocol for the peripheral bus. Bridge circuit 216 interfaces with peripheral 208-1 through peripheral bus 218-1 and with peripheral 208-2 through peripheral bus 218-2. Communication between microprocessor 202, bridge circuit 216 and peripheral 208-1 is coordinated by a clock signal from clock source 220 (also received by memory 204, address decoder 206, and external bus interface 209).
Peripheral 208-2 receives a clock signal from clock source 222, which differs from clock source 220. Bridge circuit 216 receives clock source 222 and resynchronizes signals between microprocessor 202, which operates at the timing of clock source 220, and peripheral 208-2. In order to resynchronize, microcontroller 200 duplicates some parts of the bus (particularly the address bus), which in turn requires more power.
What is needed is a method and system for resynchronizing signals between peripherals at different clock frequencies that uses fewer components and reduce power consumption.